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YFLEX(TM) Data

Comparison between YFLEX and through-hole FPC

Through-hole soldering

Through-hole soldering

Bump lamination

Bump lamination

Bump Lamination Process
2-layer double-sided circuit board manufacturing process

Bump Lamination Process

Layer Structure of double sided YFLEXTM

YFLEX(TM) Layer Structure

Example of YFLEX structure

Materials
Substrate
Liquid Crystal Polymer (25 or 50 µm)
Conductor
Copper (12,18,or 35µm)
Bump
Silver Filled Resin
Cover Lay
Thermoset Resist, Photo Sensitive Resist, Polyimide

Design Rules

Standard Minimum
Width (Trace/Space) 60/60µm 30/30µm
Bump Diameter 250µm 150µm
Land Diameter 400µm 250µm
Maximum Current per Bump 100mA 50mA
Suerface Process Au Flash Plating
Au Bonding Plating

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LCD moisture absorption and dielectric constact data

High humidity decreasing rate of voltage proof (Vx)

High humidity decreasing rate (Vx)

Dielectric constant

Dielectric constant

Expansion rate

Expansion rate

LCD test data


Conditions Results
Resistance per a bump Room temperature/humidity 6mΩ or less
Temperature cycle test - 55°C to + 125°C, 1000cycle Resistance change: Within 6%
High temperature storage test + 125°C, 1000h Resistance change: Within 6%
Low temperature storage test - 40°C, 1000h Resistance change: Within 6%
High temperature/humidity test 85°C, 90%RH, 1000h Resistance change: Within 6%
Ion migration test 40°C, 90%RH, 60VDC, 1000h No insulation damage
Peeling test 90°peels (Copper t=35µm) >0.8KN/m
Soldering thermal test 260°C, 20sec No damage
Dielectric constant (1GHz) Bridge method* 2.8
Dielectric dissipation factor (1GHz) Bridge method* 0.0025
Moisture absorption 23°C, 24h* <0.04%
Thermal expansion TMA method* (Thermo-Mechanical Analysis) x: 12ppm/°C
y: 16ppm/°C
z: Approx. 100ppm/°C

* Measuring method: JIS C 6481-1996

  • The data are for reference only. Yamaichi Electronics Co., Ltd. does not gurantee the above-mentioned values.

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